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@ -69,6 +69,41 @@ static void atomic_add(struct atomic *atom, uint32_t id, uint32_t prop, uint64_t
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}
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}
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static bool create_gamma_lut_blob(struct wlr_drm_backend *drm,
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struct wlr_drm_crtc *crtc, uint32_t *blob_id) {
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if (crtc->gamma_table_size == 0) {
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*blob_id = 0;
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return true;
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}
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uint32_t size = crtc->gamma_table_size;
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uint16_t *r = crtc->gamma_table;
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uint16_t *g = crtc->gamma_table + size;
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uint16_t *b = crtc->gamma_table + 2 * size;
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struct drm_color_lut *gamma = malloc(size * sizeof(struct drm_color_lut));
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if (gamma == NULL) {
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wlr_log(WLR_ERROR, "Failed to allocate gamma table");
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return false;
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}
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for (size_t i = 0; i < size; i++) {
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gamma[i].red = r[i];
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gamma[i].green = g[i];
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gamma[i].blue = b[i];
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}
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if (drmModeCreatePropertyBlob(drm->fd, gamma,
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size * sizeof(struct drm_color_lut), blob_id) != 0) {
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wlr_log_errno(WLR_ERROR, "Unable to create property blob");
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free(gamma);
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return false;
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}
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free(gamma);
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return true;
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}
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static void plane_disable(struct atomic *atom, struct wlr_drm_plane *plane) {
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uint32_t id = plane->id;
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const union wlr_drm_plane_props *props = &plane->props;
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@ -126,6 +161,24 @@ static bool atomic_crtc_pageflip(struct wlr_drm_backend *drm,
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}
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}
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if (crtc->pending & WLR_DRM_CRTC_GAMMA_LUT) {
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// Fallback to legacy gamma interface when gamma properties are not available
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// (can happen on older Intel GPUs that support gamma but not degamma).
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if (crtc->props.gamma_lut == 0) {
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if (!drm_legacy_crtc_set_gamma(drm, crtc)) {
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return false;
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}
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} else {
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if (crtc->gamma_lut != 0) {
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drmModeDestroyPropertyBlob(drm->fd, crtc->gamma_lut);
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}
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if (!create_gamma_lut_blob(drm, crtc, &crtc->gamma_lut)) {
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return false;
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}
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}
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}
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uint32_t flags = DRM_MODE_PAGE_FLIP_EVENT;
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if (modeset) {
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flags |= DRM_MODE_ATOMIC_ALLOW_MODESET;
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@ -142,6 +195,7 @@ static bool atomic_crtc_pageflip(struct wlr_drm_backend *drm,
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}
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atomic_add(&atom, crtc->id, crtc->props.mode_id, crtc->mode_id);
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atomic_add(&atom, crtc->id, crtc->props.active, 1);
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atomic_add(&atom, crtc->id, crtc->props.gamma_lut, crtc->gamma_lut);
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set_plane_props(&atom, drm, crtc->primary, crtc->id, 0, 0);
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if (crtc->cursor) {
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if (crtc->cursor->cursor_enabled) {
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@ -195,45 +249,6 @@ static bool atomic_crtc_set_cursor(struct wlr_drm_backend *drm,
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return true;
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}
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static bool atomic_crtc_set_gamma(struct wlr_drm_backend *drm,
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struct wlr_drm_crtc *crtc, size_t size,
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uint16_t *r, uint16_t *g, uint16_t *b) {
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// Fallback to legacy gamma interface when gamma properties are not available
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// (can happen on older Intel GPUs that support gamma but not degamma).
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if (crtc->props.gamma_lut == 0) {
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return legacy_iface.crtc_set_gamma(drm, crtc, size, r, g, b);
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}
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struct drm_color_lut *gamma = malloc(size * sizeof(struct drm_color_lut));
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if (gamma == NULL) {
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wlr_log(WLR_ERROR, "Failed to allocate gamma table");
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return false;
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}
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for (size_t i = 0; i < size; i++) {
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gamma[i].red = r[i];
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gamma[i].green = g[i];
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gamma[i].blue = b[i];
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}
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if (crtc->gamma_lut != 0) {
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drmModeDestroyPropertyBlob(drm->fd, crtc->gamma_lut);
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}
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if (drmModeCreatePropertyBlob(drm->fd, gamma,
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size * sizeof(struct drm_color_lut), &crtc->gamma_lut)) {
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free(gamma);
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wlr_log_errno(WLR_ERROR, "Unable to create property blob");
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return false;
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}
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free(gamma);
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struct atomic atom;
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atomic_begin(crtc, &atom);
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atomic_add(&atom, crtc->id, crtc->props.gamma_lut, crtc->gamma_lut);
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return atomic_end(drm->fd, 0, &atom);
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}
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static size_t atomic_crtc_get_gamma_size(struct wlr_drm_backend *drm,
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struct wlr_drm_crtc *crtc) {
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if (crtc->props.gamma_lut_size == 0) {
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@ -254,6 +269,5 @@ const struct wlr_drm_interface atomic_iface = {
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.conn_enable = atomic_conn_enable,
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.crtc_pageflip = atomic_crtc_pageflip,
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.crtc_set_cursor = atomic_crtc_set_cursor,
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.crtc_set_gamma = atomic_crtc_set_gamma,
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.crtc_get_gamma_size = atomic_crtc_get_gamma_size,
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};
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